1. Field of the Invention
This invention relates to a semiconductor chip package.
2. Description of the Related Art
Higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As these goals are achieved, microelectronic chips become smaller. Of course, the goal of greater packaging density requires that the entire microelectronic chip package be equal to or only slightly larger (about 10% to 30%) than the size of the microelectronic chip itself. Such microelectronic chip package is called a “chip scale package (CSP)”.
As shown in FIG. 1, a conventional chip scale package comprises a microelectronic chip 102 and a build-up structure directly formed on the active surface 104 of the microelectronic chip 102. The build-up structure may include a dielectric layer 106 disposed on the active surface 104 of the microelectronic chip. Conductive traces 108 may be formed on the dielectric layer 106, wherein a portion of each conductive trace 108 contacts at least one contact pad 112 on the active surface 104 of the microelectronic chip. External contacts, such as solder balls or conductive pins for contact with an external component (not shown), may be fabricated to electrically contact at least one conductive trace 108. FIG. 1 illustrates the external contacts as solder balls 114 where are surrounded by a solder mask material 116 on the dielectric layer 106. However, in such kind of chip scale package, the surface area provided by the active surface 104 of the microelectronic chip generally does not provide enough surface for all of the external contacts needed to contact the external component.